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1CY 7C40 9A
CY7C408A CY7C409A
64 x 8 Cascadable FIFO 64 x 9 Cascadable FIFO
Features
* * * * * * * * * * * 64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory 35-MHz shift in and shift out rates Almost Full/Almost Empty and Half Full flags Dual-port RAM architecture Fast (50-ns) bubble-through Independent asynchronous inputs and outputs Output enable (CY7C408A) Expandable in word width and FIFO depth 5V 10% supply TTL complete Capable of withstanding greater than 2001V electrostatic discharge voltage * 300-mil, 28-pin DIP same order as it was stored on the DO0 - DO8 output pins under the control of the shift out (SO) input when the output ready (OR) control signal is HIGH. If the FIFO is full (IR LOW), pulses at the SI input are ignored; if the FIFO is empty (OR LOW), pulses at the SO input are ignored. The IR and OR signals are also used to connect the FIFOs in parallel to make a wider word or in series to make a deeper buffer, or both. Parallel expansion for wider words is implemented by logically ANDing the IR an OR outputs (respectively) of the individual FIFOs together (Figure 5). The AND operation insures that all of the FIFOs are either ready to accept more data (IR HIGH) or ready to output data (OR HIGH) and thus compensate for variations in propagation delay times between devices. Serial expansion (cascading) for deeper buffer memories is accomplished by connecting data outputs of the FIFO closet to the data source (upstream device) to the data inputs of the following (downstream) FIFO (Figure 4). In addition, to insure proper operation, the SO signal of the upstream FIFO must be connected to the OR output of the upstream FIFO. In this serial expansion configuration, the IR and OR signals are used to pass data through the FIFOs. Reading and writing operations are completely asynchronous, allowing the FIFO to be used as a buffer between two digital machines of widely differing operating frequencies. The high shift in and shift out rates of these FIFOs, and their throughput rate due to the fast bubblethrough time, which is due to their dual-port RAM architecture, make them ideal for high-speed communications and controllers.
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or 9-bit wide first-in first-out (FIFO) buffer memories. In addition to the industry-standard handshaking signals, almost full/almost empty (AFE) and half-full (HF) flags are provided. AFE is HIGH when the FIFO is almost full or almost empty, otherwise AFE is LOW. HF is HIGH when the FIFO is half full, otherwise HF is LOW. The CY7C408A has an output enable (OE) function. The memory accepts 8- or 9-bit parallel words as its inputs (DI0 - DI8) under the control of the shift in (SI) input when the input ready (IR) control signal is HIGH. The data is output, in the
Logic Block Diagram
SI IR INPUT CONTROL LOGIC WRITE POINTER WRITEMULTIPLEXER ALMOST FULL/ ALMOST EMPTY HALF FULL AFE HF DO 0 . . . DO 7 DATAOUT
Pin Configurations
AFE HF IR SI DI 0 DI 1 GND 1 28 2 27 3 26 4 25 5 24 6 23 7C408A 7 7C409A 22 21 8 9 20 10 19 11 18 12 17 13 16 15 14 VCC MR SO OR DO0 DO1 GND DO2 DO3 DO4 DO5 DO6 DO7 OE (7C408A) DO8 (7C409A) C408A-3
DI 0 . . . DI 7 (7C409A)DI 8
DATA IN
MEMORY ARRAY
READ MULTIPLEXER MR MASTER RESET READ POINTER OUTPUT CONTROL LOGIC C408A-1
DI 2 DI 3 DO 8 (7C409A) DI 4 DI 5 DI 6 OE (7C408A) DI 7 OR (7C408A) NC (7C409A) DI8 SO
Flag Definitions HF L L H H AFE H L L H Words Stored 0-8 9 - 31 32 - 55 56 - 64
DI 0 DI 1 GND DI 2 DI 3 DI 4 DI 5
4 3 2 1 28 27 26 25 5 24 6 23 7 7C408A 22 8 7C409A 21 9 20 10 19 11 12 13 14 15 1617 18
OR DO 0 DO 1 GND DO 2 DO 3 DO 4
C408A-2
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1986 - Revised July 1994
CY7C408A CY7C409A
Selection Guide
7C408A-15 7C409A-15 Maximum Shift Rate (MHz) Maximum Operating Current (mA)[1] Commercial Military 15 115 140 7C408A-25 7C409A-25 25 125 150 7C408A-35 7C409A-35 35 135 N/A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State (7C408A)...................................-0.5V to +7.0V DC Input Voltage .................................................-3.0V to +7.0V
Power Dissipation.......................................................... 1.0W Output Current, into Outputs (Low) ............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015)
Operating Range
Range Commercial Military[2] Ambient Temperature 0C to +70C -55C to +125C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted) [3]
Parameter VOH VOL VIH VIL IIX IOS ICCQ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current[4] Quiescent Power Supply Current Power Supply Current GND < VI < VCC VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA VIN < VIL, VIN > VIH ICC = ICCQ + 1 mA/MHz x (fSI + fSO)/2 Commercial Military Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -3.0 -10 Min. 2.4 0.4 VCC 0.8 +10 -90 100 125 Max. Unit V V V V A mA mA
Capacitance[5]
Parameter CIN COUT
Notes: 1. 2. 3. 4. 5.
Description Input Capacitance Output Capacitance
Test Conditions TA = 25C, f = 1 MHz, VCC = 4.5V
Max. 5 7
Unit pF pF
ICC = ICCQ + 1 mA/MHz x (fSI + fSO )/2 TA is the "instant on" case temperature. See the last page of this specification for Group A subgroup testing information. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 482 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: 30 pF R2 256 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 256 GND 5 ns R1 482 3.0V 90% 10% 90% 10% 5 ns ALL INPUT PULSES
(a)
(b)
C408A-4 C408A-5
THEVENIN EQUIVALENT 167 1.73V
C408A-6
OUTPUT
2
CY7C408A CY7C409A
Switching Characteristics Over the Operating Range[3, 6]
Test Conditions Note 7 Note 7 Note 7 Note 8 Note 8 23 25 0 30 35 40 Note 7 Note 7 23 25 35 40 0 0 10 Note 9 Note 9 Note 10 Note 11 Note 12 Note 7 5 30 6 6 35 35 65 65 65 65 55 25 55 55 Note 13 55 55 55 28 45 10 45 45 45 45 45 20 65 0 0 10 5 20 6 6 30 30 55 55 55 55 35 10 35 35 35 35 35 16 60 11 24 21 23 0 0 10 5 20 6 6 25 25 45 45 45 45 50 7C408A-15 7C409A-15 Min. Max. 15 11 24 0 20 21 23 9 17 15 16 7C408A-25 7C409A-25 Min. Max. 25 9 17 0 12 15 16 7C408A-35 7C409A-35 Min. Max. 35 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter fO tPHSI tPLSI tSSI tHSI tDLIR tDHIR tPHSO tPLSO tDLOR tDHOR tSOR tHSO tBT tSIR tHIR tPIR tPOR tDLZOE tDHZOE tDHHF tDLHF tDLAFE tDHAFE tPMR tDSI tDOR tDIR tLZMR tAFE tHF tOD
Description Operating Frequency SI HIGH Time SI LOW Time Data Set-Up to SI Data Hold from SI Delay, SI HIGH to IR LOW Delay, SI LOW to IR HIGH SO HIGH Time SO LOW Time Delay, SO HIGH to OR LOW Delay, SO LOW to OR HIGH Data Set-Up to OR HIGH Data Hold from SO LOW Fall-through, Bubble-back Time Data Set-Up to IR Data Hold from IR Input Ready Pulse HIGH Output Ready Pulse HIGH OE LOW to LOW Z (7C408A) OE HIGH to HIGH Z (7C408A) SI LOW to HF HIGH SO LOW to HF LOW SO or SI LOW to AFE LOW SO or SI LOW to AFE HIGH MR Pulse Width MR HIGH to SI HIGH MR LOW to OR LOW MR LOW to IR HIGH MR LOW to Output LOW MR LOW to AFE HIGH MR LOW to HF LOW SO LOW to Next Data Out Valid
Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I OL/IOH and 30-pF load capacitance, as in parts (a) and (b) of AC Test Loads and Waveforms. 7. 1/f O > (tPHSI + tPLSI ), 1/fO > (tPHSO + tPLSO). 8. tSSI and tHSI apply when memory is not full. 9. tSIR and tHIR apply when memory is full, SI is high and minimum bubble-through (tBT) conditions exist. 10. At any given operating condition tPIR > (t PHSO required). 11. At any given operating condition tPOR > (tPHSI required). 12. tDHZOE and tDLZOE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. tDHZOE transition is measured 500 mV from steady-state voltage. tDLZOE transition is measured 100 mV from steady-state voltage. These parameters are guaranteed and not 100% tested. 13. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO.
3
CY7C408A CY7C409A
Switching Waveforms
Data In Timing Diagram
I/fO SHIFT IN tPHSI INPUT READY tHSI DATA IN tSSI tDLIR NOTE 14 tPLSI
I/fO
tDHIR
tDLAFE
AFE
HF
(LOW)
C408A-7
Data Out Timing Diagram
I/fO SHIFT OUT NOTE 15 tPHSO OUTPUT READY tHSO DATA OUT tDLOR tPLSO
I/fO
tDHOR
tSOR
tOD HF (LOW) tDHAFE AFE
C408A-8
Notes: 14. FIFO contains 8 words. 15. FIFO contains 9 words.
4
CY7C408A CY7C409A
Switching Waveforms (continued)
Data In Timing Diagram
I/fO SHIFT IN tPHSI INPUT READY tHSI DATA IN tSSI tDLIR NOTE 16 tPLSI tDHIR I/fO
AFE
(LOW) tDHHF
HF
C408A-9
Data Out Timing Diagram
I/fO SHIFT OUT NOTE 17 tPHSO OUTPUT READY tHSO DATA OUT tOD HF tDLHF AFE (LOW)
C408A-10
I/fO
tPLSO
tDHOR
tDLOR
tSOR
Output Enable (CY7C408A only)
OUTPUT ENABLE tDHZOE DATA OUT NOTE 12
C408A-11
tDLZOE
Notes: 16. FIFO contains 31 words. 17. FIFO contains 32 words.
5
CY7C408A CY7C409A
Switching Waveforms (continued)
Data In Timing Diagram
I/fO SHIFT IN tPHSI INPUT READY tHSI DATA IN tSSI HF AFE
C408A-12
I/fO
NOTE 18 tPLSI tDHIR
tDLIR
(HIGH)
tDHAFE
Data Out TimingDiagram
I/fO SHIFT OUT NOTE 19 tPHSO OUTPUT READY tHSO DATA OUT tOD AFE tDLAFE HF (HIGH)
C408A-13
I/fO
tPLSO
tDHOR
tDLOR
tSOR
Bubble-Back, Data Out To Data In Diagram
SHIFT OUT NOTE 20
SHIFT IN tBT INPUT READY tPIR DATA IN tSIR
Notes: 18. FIFO contains 55 words. 19. FIFO contains 56 words. 20. FIFO contains 64 words.
tHIR
C408A-14
6
CY7C408A CY7C409A
Switching Waveforms (continued)
Fall-Through, Data In to Data Out Diagram
SHIFT IN
NOTE 21
SHIFT OUT tBT OUTPUT READY tSOR DATA OUT tPOR
C408A-15
Master Reset Timing Diagram
tPMR MASTER RESET tDIR INPUT READY tDOR
OUTPUT READY tDSI SHIFT IN tLZMR DATA OUT
HF
tHF
AFE
tAFE
C408A-16
Notes: 21. FIFO is empty.
7
CY7C408A CY7C409A
Architecture of the CY7C408A and CY7C409A
The CY7C408A and CY7C409A FIFOs consist of an array of 64 words of 8 or 9 bits each (which are implemented using a dual-port RAM cell), a write pointer, a read pointer, and the control logic necessary to generate the handshaking (SI/IR, SO/OR) signals as well as the almost full/almost empty (AFE) and half full (HF) flags. The handshaking signals operate in a manner identical to those of the industry standard CY7C401/402/403/404 FIFOs. tion, which is signified by the OR signal being LOW at the same time that the IR signal is HIGH. In this condition, the data outputs (DO0 - DO8) will be LOW. The AFE flag will be HIGH and the HF flag will be LOW.
Shifting Data Into the FIFO
The availability of an empty location is indicated by the HIGH state of the input ready (IR) signal. When IR is HIGH a LOW to HIGH transition on the shift in (SI) pin will clock the data on the DI0 - DI8 inputs into the FIFO. Data propagates through the device at the falling edge of SI. The IR output will then go LOW, indicating that the data has been sampled. The HIGH-to-LOW transition of the SI signal initiates the LOW-to-HIGH transition of the IR signal if the FIFO is not full. If the FIFO is full, IR will remain LOW.
Dual-Port RAM
The dual-port RAM architecture refers to the basic memory cell used in the RAM. The cell itself enables the read and write operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. A second benefit is that the time required to increment the read and write pointers is much less than the time that would be required for data to propagate through the memory, which it would have to do if the memory were implemented using the conventional register array architecture.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated by the HIGH state of the output ready (OR) signal. After the FIFO is reset all data outputs (DO0 - DO8) will be in the LOW state. As long as the FIFO remains empty, the OR signal will be LOW and all SO pulses applied to it will be ignored. After data is shifted into the FIFO, the OR signal will go HIGH. The external control logic (designed by the user) should use the HIGH state of the OR signal to generate a SO pulse. The data outputs of the FIFO should be sampled with edge-sensitive type D flip-flops (or equivalent), using the SO signal as the clock input to the flip-flop.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the output of an initially empty FIFO is defined as the fall-through time. The time required for an empty location to propagate from the output to the input of an initially full FIFO is defined as the bubble-back time. The maximum rate at which data can be passed through the FIFO (called the throughput) is limited by the fall-through time when it is empty (or near empty) and by the bubble-back time when it is full (or near full). The conventional definitions of fall-through and bubble-back do not apply to the CY7C408A and CY7C409A FIFOs because the data is not physically propagated through the memory. The read and write pointers are incremented instead of moving the data. However, the parameter is specified because it does represent the worst-case propagation delay for the control signals. That is, the time required to increment the write pointer and propagate a signal from the SI input to the OR output of an empty FIFO or the time required to increment the read pointer and propagate a signal from the SO input to the IR output of a full FIFO.
AFE and HF Flags
Two flags, almost full/almost empty (AFE) and half full (HF), describe how many words are stored in the FIFO. AFE is HIGH when there are 8 or fewer or 56 or more words stored in the FIFO. Otherwise the AFE flag is LOW. HF is HIGH when there are 32 or more words stored in the FIFO, otherwise the HF flag is LOW. Flag transitions occur relative to the falling edges of SI and SO (Figures 1 and 2). Due to the asynchronous nature of the SI and SO signals, it is possible to encounter specific timing relationships which may cause short pulses on the AFE and HF flags. These pulses are entirely due to the dynamic relationship of the SI and SO signals. The flags, however, will always settle to their correct state after the appropriate delay (tDHAFE, tDLAFE, tDHHF, or tDLHF). Therefore, use of level-sensitive rather than edge-sensitive flag detection devices is recommended to avoid false flag encoding.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset (MR) signal. This causes the device to enter the empty condiEMPTY 1 SHIFT IN 2 8 9 10 31
32
33
55
56
57
FULL 64
HF
AFE
C408A-17
Figure 1. Shifting Words In.
8
CY7C408A CY7C409A
Possible Minimum Pulse Width Violation at the Boundary Conditions If the handshaking signals IR and OR are not properly used to generate the SI and SO signals, it is possible to violate the minimum (effective) SI and SO positive pulse widths at the full and empty boundaries.
3). Two things should be noted when this configuration is implemented.
Secondly, the frequency at the cascade interface is less than the 35 MHz rate at which the external clocks may operate. Therefore, the first device has its data shifted in faster than it is shifted out, and eventually this device becomes momentarily full. When this occurs, the maximum sustainable external clock frequency changes from 35 MHz to the cascade interface frequency.[28] When data packets[29] are transmitted, this phenomenon does not occur unless more than three FIFOs are depth cascaded. For example, if two FIFOs are cascaded, a packet of 127 (=2 x 63 + 1) words may be shifted in at up to 35 MHz and then the entire packet may be shifted out at up to 35 MHz.
EMPTY 1
Cascading the 7C408/9A-35 Above 25 MHz
First, the capacity of N cascaded FIFOs is decreased from N x 64 to (N x 63) + 1. If cascaded FIFOs are to be operated with an external clock rate greater than 25 MHz, the interface IR signal must be inverted before being fed back to the interface SO pin (Figure
FULL 64 SHIFT OUT HF
63
56
55
54
32
31
30
9
8
7
AFE
C408A-18
Figure 2. Shifting Words Out.
A IRX SIX DINX IR SI DIN 1 2 UPSTREAM DOWNSTREAM N
C408A-19
B SO OR IR SI SO OR IR SI
C SO OR SOX ORX DOUTX
IR SI
Figure 3. Cascaded Configuration Above 25 MHz. 128 x 9 Configuration
HF/AFE SHIFT IN INPUT READY SI IR DI0 DI1 DI2 DATA IN DI3 DI4 DI5 DI6 DI7 DI8 OR SO DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 HF/AFE SI IR DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 OR SO DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DATA OUT OUTPUT READY SHIFT OUT
MR
MR
MR
C408A-20
Figure 4. Cascaded Configuration at or below 25 MHz [22,23,24,25,26].
9
CY7C408A CY7C409A
192 x 27 Configuration
HF/AFE IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 COMPOSITE INPUT READY IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 HF/AFE SHIFT OUT
MR
MR
MR
COMPOSITE OUTPUT READY
MR
MR
MR
SHIFT IN
IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8
IR SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8
MR
SO OR DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 MR
C408A-21
Figure 5. Depth and Width Expansion[23,24,25,26,27].
Notes: 22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. 23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output. 24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs. 25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for one internal cycle (at least tPOR) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW. 26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW. 27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output ready flags. This need is due to the variation of delays of the FIFOs 28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used. 29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring. The complement of this holds when data is shifted out as a packet.
10
CY7C408A CY7C409A
If data is to be shifted out simultaneously with the data being shifted in, the concept of "virtual capacity" is introduced. Virtual capacity is simply how large a packet of data can be shifted in at a fixed frequency, e.g., 35 MHz, simultaneously with data being shifted out at any given frequency. Figure 6 is a graph of packet size[30] vs. shift out frequency (f SOx) for two different values of shift in frequency (fSIx) when two FIFOs are cascaded.
400 350 300 250 200 150 100 50 0 0 4 8 12 16 20 24 28 32 36
C408A-22
The exact complement of this occurs if the FIFOs initially contain data and a high shift out frequency is to be maintained, i.e., a 35 MHz fSOx can be sustained when reading data packets from devices cascaded two or three deep.[31] If data is shifted in simultaneously, Figure 6 applies with fSIx and fSOx interchanged.
fSIx =30MHz
fSIx =35MHz
OUTPUT RATE(fSOx) OF BOTTOM FIFO (MHz)
Figure 6. Virtual Capacity vs. Output Rate for Two FIFOs Cascaded Using an Inverter.
Notes: 30. These are typical packet sizes using an inverter whose delay is 4 ns. 31. Only devices with the same speed grade are specified to cascade together.
11
CY7C408A CY7C409A
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 1.0 1.4 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 60 50 1.2 40 0.8 1.0 30 20 VCC =5.5V VIN =5.0V 25 125 10 0 0.0 VCC =5.0V TA =25C 1.0 2.0 3.0 4.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
0.6
VIN =5.0V TA =25C 4.5 5.0 5.5 6.0
0.8
0.4 4.0
0.0 -55
SUPPLYVOLTAGE(V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
NORMALIZED FREQUENCY vs. SUPPLY VOLTAGE 1.3 1.2 1.1 1.2 1.0 1.0 0.9 0.8 0.7 4.0 4.5 5.0 5.5 6.0 0.8 0.6 -55 1.6 1.4
NORMALIZED FREQUENCY vs. AMBIENT TEMPERATURE 140 120 100 80 60 40 20 25 125
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
0 0.0
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
OUTPUT VOLTAGE (V)
TYPICAL FREQUENCY CHANGE vs. OUTPUT LOADING 1.6 1.5 1.4 0.9 1.3 0.8 1.2 1.1 1.0 0 200 400 600 800 1000 0.7 0.0 1.1 1.0
NORMALIZED I CC vs. FREQUENCY
0
5
10
15
20
25
30
35
C408A-23
CAPACITANCE (pF)
FREQUENCY (MHz)
12
CY7C408A CY7C409A
Ordering Information
Frequency (MHz) 15 Ordering Code CY7C408A-15PC CY7C408A-15VC CY7C408A-15DMB CY7C408A-15LMB 25 CY7C408A-25PC CY7C408A-25VC CY7C408A-25DMB CY7C408A-25LMB 35 CY7C408A-35PC CY7C408A-35VC Package Name P21 V21 D22 L64 P21 V21 D22 L64 P21 V21 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ Commercial Military Commercial Military Operating Range Commercial
Frequency (MHz) 15
Ordering Code CY7C409A-15PC CY7C409A-15VC CY7C409A-15DMB CY7C409A-15LMB
Package Name P21 V21 D22 L64 P21 V21 D22 L64 P21 V21
Package Type 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) CerDIP 28-Square Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead (300-Mil) Molded SOJ
Operating Range Commercial Military Commercial Military Commercial
25
CY7C409A-25PC CY7C409A-25VC CY7C409A-25DMB CY7C409A-25LMB
35
CY7C409A-35PC CY7C409A-35VC
13
CY7C408A CY7C409A
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters VOH VOL VIH VIL Max. IIX IOZ IOS ICCQ Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 fO tPHSI tPLSI tSSI tHSI tDLIR tDHIR tPHSO tPLSO tDLOR tDHOR tSOR tHSO tBT tSIR tHIR tPIR tPOR tSIIR tSOOR tDLZOE tDHZOE tDHHF tDLHF tDLAFE tDHAFE tB tOD tPMR tDSI tDOR tDIR tLZMR tAFE tHF
Switching Characteristics
Parameters Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00059-G
14
CY7C408A CY7C409A
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config.A
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
28-Lead (300-Mil) Molded DIP P21
15
CY7C408A CY7C409A
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
(c) Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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